PCIe接口相對來講還是打交道比較多的接口。無論是Intel還是Xilinx的IP也都接觸到過。談及PCIe，就不可避免地涉及Bar空間。當然廠商的IP還是包裝的可以的，我們直接配置就行。但在使用時關于Bar空間的配置，往往牽涉到這么幾個概念：

IO/Mem

Prefetchable

32位/64位

早前這東西不假思索，抄抄之前的設計照著配置就好了。乍看pcieext-cocotb中的實現(xiàn)，不禁思索，這些參數(shù)軟件是如何識別的呢？像下面EP常涉及的配置空間：

配置空間中所涉及到的只有6個Base Address Registers,似乎并無很明顯的指示～ 》協(xié)議解讀

先來看看Spec中關于Base Address Registers的定義：

關于如何區(qū)分是Mem空間還是IO空間，Spec中定義了：

bit0:為1表示Memory Space，為0則表示I/O Space。

(I/O空間僅支持32位，且現(xiàn)在PCIe設備里也較少使用，這里不再展開，感興趣小伙伴可自行翻看Spec)

對于Memory類型空間，bit[3:0]均為只讀。在bit[2:1]中定義了Memory類型空間

可見，當bit[2]為1時表示64位地址空間，否則為32位地址空間。

而當bit[3]為1時，表示該Bar空間為Prefetchable，為0則不是非prefetchable。

看到這里,上面的疑問也基本可以解答了。在cocotbext-pcie中的配置方式也有所驗證：

》Prefetchable

關于Prefetchable這個屬性，一直也沒有非常清晰的認識。按照Spec中的定義：

A Function is permittedto mark a range as prefetchable if there are no side effects on reads, the Function returns all bytes on reads regardless ofthe byte enables, and host bridges can merge processor writes into this rangewithout causing errors.

Any device that has a range that behaves like normal memory should mark the range as prefetchable. A linear frame buffer in a graphics device is an exampleof a range that should be marked prefetchable.

一般而言，在PCIe設備里，Bar空間基本用于實現(xiàn)寄存器讀寫，是基本符合上面所描述的情況的，所以配置成prefetchable還是有必要的。而且在spec中，也提到了： PCI Express adapters with Memory Space BARs that request a large amount of non-prefetchable Memory Space(e.g., over 64 MB) may cause shortages of that Space on certain scalable platforms, since many platforms supporta total of only 1 GB or less of non-prefetchable Memory Space.This may limit the number of such adapters that

can be supported on those platforms. For this reason, it is especially encouraged for BARs requesting largeamounts of Memory Space to have their Prefetchable bit Set, since prefetchable Memory Space is more bountifulon most scalable platforms.

On PCI Express systems that meet the criteria enumerated below, setting the Prefetchable bit in a candidate BARwill still permit correct operation even if the BAR’s range includes some locations that have read side-effects orcannot tolerate write merging. This is primarily due to the fact that PCI Express Memory Reads always contain an

explicit length, and PCI Express Switches never prefetch or do byte merging. Generally only 64-bit BARs are goodcandidates, since only Legacy Endpoints are permitted to set the Prefetchable bit in 32-bit BARs, and mostscalable platforms map all 32-bit Memory BARs into non-prefetchable Memory Space regardless of thePrefetchable bit value.

這里貼上Spec中的原話，總結起來：盡可能配置成64 bit prefetchable.

》Bar空間的初始化

對于Bar空間，其核心除了上述的屬性檢測外另一重點便是為Bar空間分配指定大小的地址空間。

對于Base Address Registers，Bar空間的大小只能配置成2的n次方。以32位Memory 空間為例，其可配置的范圍是16Byte～2GB(低四bit用于設置Bar空間屬性)。

對于指定大小所占用的位，其只讀并且始終為0，若沒有被使用，則其會返回全0。在初始化時軟件可以向Bar空間寫全1然后回讀。

對于讀會的數(shù)據(jù)，將低4bit清零，然后所有bit取反后加1即為對應的Bar空間大小。分配好地址空間好將Base地址寫回到Base Address Registers中～

審核編輯：劉清