DSP的特點(diǎn)  ：

什么叫做DSP？DSP（digital Signal Processor）中文：數(shù)字信號(hào)處理器。

        對(duì)于沒(méi)有使用過(guò)DSP的初學(xué)者來(lái)說(shuō)，第一個(gè)困惑就是DSP其他的嵌入式處理器究竟有什么不同，它和單片機(jī)，ARM有什么區(qū)別。事實(shí)上，DSP也是一種嵌入式處理器，它完全可以完成單片機(jī)的功能。 
        唯一的重要的區(qū)別在于DSP支持單時(shí)鐘周期的"乘-加"運(yùn)算。這幾乎是所有廠家的DSP芯片的一個(gè)共有特征。幾乎所有的DSP處理器的指令集中都會(huì)有一條MAC指令，這條指令可以把兩個(gè)操作數(shù)從RAM中取出相乘，然后加到一個(gè)累加器中，所有這些操作都在一個(gè)時(shí)鐘周期內(nèi)完成。擁有這樣一條指令的處理器就具備了DSP功能。 
       具有這條指令就稱之為數(shù)字信號(hào)處理器的原因在于，所有的數(shù)字信號(hào)處理算法中最為常見的算術(shù)操作就是"乘-加"。這是因?yàn)閿?shù)字信號(hào)處理中大量使用了內(nèi)積，或稱"點(diǎn)積"的運(yùn)算。無(wú)論是FIR濾波，F(xiàn)FT，信號(hào)相關(guān)，數(shù)字混頻，下變頻。所有這些數(shù)字信號(hào)處理的運(yùn)算經(jīng)常是將輸入信號(hào)與一個(gè)系數(shù)表或者與一個(gè)本地參考信號(hào)相乘然后積分（累加），這就表現(xiàn)為將兩個(gè)向量（或稱序列）進(jìn)行點(diǎn)積，在編程上就變成將輸入的采樣放在一個(gè)循環(huán)buffer里，本地的系數(shù)表或參考信號(hào)也放在一個(gè)buffer里，然后使用兩個(gè)指針指向這兩個(gè)buffer。這樣就可以在一個(gè)loop里面使用一個(gè)MAC指令將二者進(jìn)行點(diǎn)積運(yùn)算。這樣的點(diǎn)積運(yùn)算對(duì)與處理器來(lái)說(shuō)是最快的，因?yàn)閮H需一個(gè)始終周期就可以完成一次乘加。 

了解DSP的這一特點(diǎn)后，當(dāng)我們?cè)O(shè)計(jì)一個(gè)嵌入式系統(tǒng)時(shí)，首先要考慮處理器所實(shí)現(xiàn)的算法中是否有點(diǎn)積運(yùn)算，即是否要經(jīng)常進(jìn)行兩個(gè)數(shù)組的乘加，（記住數(shù)字濾波，相關(guān)等都表現(xiàn)為兩個(gè)數(shù)組的點(diǎn)積）如果有的話，每秒要做多少次，這樣就能夠決定是否采用DSP，采用多高性能的DSP了。 

Figure Ov.4 illustrates an average digital signalprocessing system with dual tagless SRAMs on-chip,an off-chip programmable ROM (e.g., PROM, EPROM, flash ROM, etc.) that holds the executable image, and an off-chip DRAM that is used for computation and holding variable data. External memory and device controllers can be used, but many embedded microprocessors already have such controllers integrated onto the CPU die. This cuts down on the system’s die count and thus cost. Note that it would be possible for the entire hierarchy to lie on the CPU die, yielding a single-chip solution called a system-on-chip. This is relatively common for systems that have limited memory requirements. Many DSPs and microcontrollers have programmable ROM embedded within them. Larger systems that require megabytes of storage (e.g., in Cisco routers, the instruction code alone is more than a 12 MB) will have increasing numbers of memory chips in the system. 

  On the right side of Figure Ov.4 is the software’s view of the memory system. The primary distinction is that, unlike general-purpose systems, is that theSRAM caches are visible as separately addressable memories, whereas they are transparent to software in general-purpose systems.