電子發燒友App
--文件名：decoder.vhd
--功能：譯碼輸出模塊，LED為共陽接法
--最后修改日期：2004.3.24
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (seg:in std_logic_vector(3 downto 0 ); --四位二進制碼輸入
q3:out std_logic_vector(6 downto 0) ); --輸出LED七段碼
end decoder;
architecture Behavioral of decoder is
begin
process(seg)
begin
case seg is
when "0000" => q3<="0000001";--0
when "0001" => q3<="1001111";--1
when "0010" => q3<="0010010";--2
when "0011" => q3<="0000110";--3
when "0100" => q3<="1001100" --4
when "0101" => q3<="0100100";--5
when "0110" => q3<="0100000";--6
when "0111" => q3<="0001111";--7
when "1000" => q3<="0000000";--8
when "1001" => q3<="0000100";--9
when others => q3<="1111111";
end case;
end process;
end Behavioral;
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例2：FPGA驅動LED動態顯示(4位)
--文件名：dynamic.vhd。
--功能：動態掃描模塊，位選信號高電平有效。
--最后修改日期：2004.3.24。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dynamic is
Port ( clk : in std_logic;
reset: in std_logic;
din1 : in std_logic_vector(6 downto 0); --譯碼后的數據信號1(4位2進制數據
通過例1中的decoder模塊譯碼得到din1,din2,din3,din4)
din2 : in std_logic_vector(6 downto 0); --譯碼后的數據信號2
din3 : in std_logic_vector(6 downto 0); --譯碼后的數據信號3
din4 : in std_logic_vector(6 downto 0); --譯碼后的數據信號4
shift: out std_logic_vector(3 downto 0); --位選信號
bus4 : out std_logic_vector(6 downto 0)); --數據信號
end dynamic;
architecture Behavioral of dynamic is
signal scan_clk:std_logic_vector(1 downto 0);
begin
process(clk,scan_clk,reset) --分頻進程
variable scan:std_logic_vector(17 downto 0);
begin
if reset='1' then
scan:="000000000000000000";
scan_clk<="00";
elsif clk'event and clk='1'then
scan:=scan+1;
end if;
scan_clk<=scan(17 downto 16);
end process;
process(scan_clk,din1,din2,din3,din4) --掃描進程
begin
case scan_clk is
when "00"=>
bus4<=din1;
shift<="0001";
when "01"=>
bus4<=din2;
shift<="0010";
when "10"=>
bus4<=din3;
shift<="0100";
when "11"=>
bus4<=din4;
shift<="1000";
when others=> bus4<="0000000";shift<="0000";
end case;
end process;
end Behavioral;
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