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TMS320C6711D 浮點數字信號處理器

數據:

描述

TMS320C67x ??的DSP(包括TMS320C6711,TMS320C6711B,TMS320C6711C,TMS320C6711D設備)構成浮點DSP家族在TMS320C6000? DSP平臺。在C6711,C6711B,C6711C和C6711D設備都是基于高性能,先進的超長指令字(VLIW)架構的德州儀器(TI)開發,使這些DSP的多通道多功能應用的絕佳選擇。

C6711D器件的時鐘頻率為200 MHz,時鐘速率高達1200萬次(MFLOPS),時鐘頻率為250 MHz,最高可達1500 MFLOPS,高效DSP編程挑戰的有效解決方案。 C6711D DSP具有高速控制器的操作靈活性和陣列處理器的數字能力。該處理器具有32個32位字長的通用寄存器和8個高度獨立的功能單元。八個功能單元提供四個浮點/定點ALU,兩個定點ALU和兩個浮點/定點乘法器。 C6711D每個周期可以產生兩個MAC,總共400 MMACS。

C6711D DSP還具有專用硬件邏輯,片上存儲器和其他片上外設。

< p> C6711D設備使用基于緩存的兩級架構,并具有功能強大且多樣化的外設集。 1級程序高速緩存(L1P)是32-Kbit直接映射高速緩存,1級數據高速緩存(L1D)是32-Kbit 2路組關聯高速緩存。 2級內存/高速緩存(L2)由512-Kbit的內存空間組成,在程序和數據空間之間共享。 L2內存可以配置為映射內存,緩存或兩者的組合。外圍組包括兩個多信道緩沖串行端口(McBSP的),兩個通用定時器,主機端口接口(HPI),和一個無縫外部存儲器接口(EMIF)能夠連接到SDRAM,SBSRAM和異步外圍設備。

C6711D有一套完整的開發工具,包括:一個新的C編譯器,一個簡化編程和調度的匯編優化器,以及一個Windows?調試器接口,用于查看源代碼執行情況。

特性

  • Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP):
      TMS320C6711D
    • Eight 32-Bit Instructions/Cycle
    • 167-, 200-, 250-MHz Clock Rates
    • 6-, 5-, 4-ns Instruction Cycle Time
    • 1000, 1200, 1500 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x? DSP Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 256M-Byte Total Addressable External Memory Space
  • 16-Bit Host-Port Interface (HPI)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola?)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffixes)
  • CMOS Technology
    • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/O, 1.4-V Internal (-250)
  • 3.3-V I/O, 1.20-V Internal

TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated as C6711D or 11D.

參數 與其它產品相比 其他 C6000 DSP

 
DSP
TMS320C6711D
1 C67x    

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