This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA).