The AS4C32M32MD1 is a four bank mobile DDR DRAM organized as 4 banks x 8M x 32. It achieves high speed data transfer rates by employing a chip architecture that pre-fetches multiple bits and then synchronizes the output data to a system clock. All of the controls， address， circuits are synchronized with the positive edge of an externally sup-plied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length， CAS latency and speed grade of the device. Additionally， the device supports low power saving features like PASR， Auto-TCSR， DPD as well as options for different drive strength. It’s ideally suit-able for mobile application.