Audience? xxix
Organization.. xxix
Suggested Readingxxx
Conventions? xxxiii
Acronyms and Abbreviations . xxxiv
Terminology Conventions .. xxxvii
Chapter 1
Overview
1.1 Overview. 1-1
1.1.1 Features 1-2
1.1.2 System Design and Programming Considerations. 1-7
1.1.2.1 Hardware Features .. 1-7
1.1.2.1.1 Replacement of XATS Signal by CSE1 Signal? 1-7
1.1.2.1.2 Addition of Half-Clock Bus Multipliers 1-7
1.1.2.2 Software Features ... 1-8
1.1.2.2.1 16-Kbyte Instruction and Data Caches .. 1-8
1.1.2.2.2 Clock Configuration Available in HID1 Register .. 1-8
1.1.2.2.3 Performance Enhancements 1-8
1.1.3 Instruction Unit . 1-9
1.1.3.1 Instruction Queue and Dispatch Unit .. 1-9
1.1.3.2 Branch Processing Unit (BPU) 1-9
1.1.4 Independent Execution Units 1-10
1.1.4.1 Integer Unit (IU) ... 1-10
1.1.4.2 Floating-Point Unit (FPU)? 1-10
1.1.4.3 Load/Store Unit (LSU) .. 1-11
1.1.4.4 System Register Unit (SRU). 1-11
1.1.4.5 Completion Unit ... 1-11
1.1.5 Memory Subsystem Support. 1-12
1.1.5.1 Memory Management Units (MMUs). 1-12
1.1.5.2 Cache Units. 1-13
1.1.6 Processor Bus Interface . 1-14
1.1.7 System Support Functions..1-14
1.1.7.1 Power Management..1-15
1.1.7.2 Time Base/Decrementer .1-15
1.1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface1-16
1.1.7.4 Clock Multiplier 1-16
1.2 PowerPC Architecture Implementation...1-16
1.3 Implementation-Specific Information .1-16
1.3.1 Programming Model..1-17
1.3.1.1 Processor Version Register (PVR) ..1-18
1.3.1.2 Hardware Implementation Register 0 (HID0)..1-18
1.3.1.3 Run_N Counter Register (Run_N) ..1-19
1.3.1.4 General-Purpose Registers (GPRs) .1-19
1.3.1.5 Floating-Point Registers (FPRs)1-19
1.3.1.6 Condition Register (CR).1-19
1.3.1.7 Floating-Point Status and Control Register (FPSCR) 1-19
1.3.1.8 Machine State Register (MSR)..1-19
1.3.1.9 Segment Registers (SRs) 1-19
1.3.1.10 Special-Purpose Registers (SPRs)...1-20
1.3.1.10.1 User-Level SPRs ..1-20
1.3.1.10.2 Supervisor-Level SPRs .1-20
1.3.2 Instruction Set and Addressing Modes1-23
1.3.2.1 PowerPC Instruction Set and Addressing Modes1-23
1.3.2.1.1 PowerPC Instruction Set ...1-23
1.3.2.1.2 Calculating Effective Addresses .1-24
1.3.2.2 Implementation-Specific Instruction Set..1-25
1.3.3 Cache Implementation..1-25
1.3.3.1 PowerPC Cache Characteristics 1-25
1.3.3.2 Implementation-Specific Cache Implementation1-26
1.3.4 Exception Model .1-27
1.3.4.1 PowerPC Exception Model ...1-27
1.3.4.2 Implementation-Specific Exception Model1-29
1.3.5 Memory Management ..1-32
1.3.5.1 PowerPC Memory Management .1-32
1.3.5.2 Implementation-Specific Memory Management.1-32
1.3.6 Instruction Timing .1-33
1.3.7 System Interface ..1-35
1.3.7.1 Memory Accesses..1-36
1.3.7.2 Signals 1-36
1.3.7.3 Signal Configuration 1-38
2.1 Register Set ..2-1
2.1.1 PowerPC Register Set .2-1
2.1.2 Implementation-Specific Registers .2-7
2.1.2.1 Hardware Implementation Registers (HID0 and HID1) ..2-7
2.1.2.2 Data and Instruction TLB Miss Address Registers
(DMISS and IMISS) 2-9
2.1.2.3 Data and Instruction TLB Compare Registers
(DCMP and ICMP) 2-9
2.1.2.4 Primary and Secondary Hash Address Registers
(HASH1 and HASH2) 2-10
2.1.2.5 Required Physical Address Register (RPA).2-11
2.1.2.6 Instruction Address Breakpoint Register (IABR) .2-11
2.1.2.7 Run_N Counter Register (Run_N)..2-12
2.2 Operand Conventions2-12
2.2.1 Floating-Point Execution Models—UISA ...2-12
2.2.2 Data Organization in Memory and Data Transfers .2-13
2.2.3 Alignment and Misaligned Accesses ..2-13
2.2.4 Floating-Point Operand2-14
2.2.5 Effect of Operand Placement on Performance.2-14
2.3 Instruction Set Summary..2-15
2.3.1 Classes of Instructions..2-16
2.3.1.1 Definition of Boundedly Undefined ..2-16
2.3.1.2 Defined Instruction Class2-16
2.3.1.3 Illegal Instruction Class .2-17
2.3.1.4 Reserved Instruction Class2-18
2.3.2 Addressing Modes.2-18
2.3.2.1 Memory Addressing.2-18
2.3.2.2 Memory Operands.2-18
2.3.2.3 Effective Address Calculation ..2-19
2.3.2.4 Synchronization 2-19
2.3.2.4.1 Context Synchronization...2-20
2.3.2.4.2 Execution Synchronization 2-20
2.3.2.4.3 Instruction-Related Exceptions ...2-20
2.3.3 Instruction Set Overview2-21
2.3.4 PowerPC UISA Instructions .2-21
2.3.4.1 Integer Instructions ..2-21
2.3.4.1.1 Integer Arithmetic Instructions ...2-22
2.3.4.1.2 Integer Compare Instructions2-22
2.3.4.1.3 Integer Logical Instructions ..2-23
2.3.4.1.4 Integer Rotate and Shift Instructions ...2-24
2.3.4.2 Floating-Point Instructions 2-25
2.3.4.2.1 Floating-Point Arithmetic Instructions.2-26
2.3.4.2.2 Floating-Point Multiply-Add Instructions2-26
2.3.4.2.3 Floating-Point Rounding and Conversion Instructions .2-27
2.3.4.2.4 Floating-Point Compare Instructions ...2-27
2.3.4.2.5 Floating-Point Status and Control Register Instructions.2-27
2.3.4.2.6 Floating-Point Move Instructions2-28
2.3.4.3 Load and Store Instructions...2-28
2.3.4.3.1 Self-Modifying Code..2-29
2.3.4.3.2 Integer Load and Store Address Generation 2-29
2.3.4.3.3 Register Indirect Integer Load Instructions..2-29
2.3.4.3.4 Integer Store Instructions ..2-30
2.3.4.3.5 Integer Load and Store with Byte-Reverse Instructions .2-31
2.3.4.3.6 Integer Load and Store Multiple Instructions..2-32
2.3.4.3.7 Integer Load and Store String Instructions...2-33
2.3.4.3.8 Floating-Point Load and Store Address Generation...2-34
2.3.4.3.9 Floating-Point Load Instructions.2-34
2.3.4.3.10 Floating-Point Store Instructions 2-34
2.3.4.4 Branch and Flow Control Instructions .2-35
2.3.4.4.1 Branch Instruction Address Calculation.2-36
2.3.4.4.2 Branch Instructions 2-36
2.3.4.4.3 Condition Register Logical Instructions 2-36
2.3.4.5 Trap Instructions2-37
2.3.4.6 Processor Control Instructions ..2-37
2.3.4.6.1 Move to/from Condition Register Instructions .2-38
2.3.4.7 Memory Synchronization Instructions—UISA2-38
2.3.5 PowerPC VEA Instructions2-39
2.3.5.1 Processor Control Instructions ..2-39
2.3.5.2 Memory Synchronization Instructions—VEA.2-40
2.3.5.3 Memory Control Instructions—VEA.2-41
2.3.5.4 External Control Instructions 2-42
2.3.6 PowerPC OEA Instructions2-42
2.3.6.1 System Linkage Instructions .2-42
2.3.6.2 Processor Control Instructions—OEA .2-42
2.3.6.2.1 Move to/from Machine State Register Instructions ...2-43
2.3.6.2.2 Move to/from Special-Purpose Register Instructions 2-43
2.3.6.3 Memory Control Instructions—OEA.2-44
2.3.6.3.1 Supervisor-Level Cache Management Instruction 2-44
2.3.6.3.2 Segment Register Manipulation Instructions ..2-45
2.3.6.3.3 Translation Lookaside Buffer Management Instructions2-45
2.3.7 Recommended Simplified Mnemonics ..2-46
2.3.8 Implementation-Specific Instructions .2-46
3.1 Instruction Cache Organization and Control3-3
3.1.1 Instruction Cache Organization...3-3
3.1.2 Instruction Cache Fill Operations 3-4
3.1.3 Instruction Cache Control 3-4
3.1.3.1 Instruction Cache Invalidation 3-4
3.1.3.2 Instruction Cache Disabling3-4
3.1.3.3 Instruction Cache Locking 3-4
3.2 Data Cache Organization and Control 3-5
3.2.1 Data Cache Organization .3-5
3.2.2 Data Cache Fill Operations ..3-5
3.2.3 Data Cache Control .3-6
3.2.3.1 Data Cache Invalidation...3-6
3.2.3.2 Data Cache Disabling.3-6
3.2.3.3 Data Cache Locking3-6
3.2.3.4 Data Cache Operations and Address Broadcasts ..3-7
3.2.4 Data Cache Touch Load Support 3-7
3.3 Basic Data Cache Operations...3-8
3.3.1 Data Cache Fill..3-8
3.3.2 Data Cache Cast-Out Operation..3-8
3.3.3 Cache Block Push Operation 3-8
3.4 Data Cache Transactions on Bus.3-8
3.4.1 Single-Beat Transactions .3-8
3.4.2 Burst Transactions.3-8
3.4.3 Access to Direct-Store Segments 3-9
3.5 Memory Management/Cache Access Mode Bits—W, I, M, and G3-10
3.5.1 Write-Through Attribute (W)3-11
3.5.2 Caching-Inhibited Attribute (I) .3-11
3.5.3 Memory Coherency Attribute (M) 3-12
3.5.4 Guarded Attribute (G) ..3-12
3.5.5 W, I, and M Bit Combinations ..3-13
3.5.5.1 Out-of-Order Execution and Guarded Memory..3-13
3.5.5.2 Effects of Out-of-Order Data Accesses ...3-14
3.5.5.3 Effects of Out-of-Order Instruction Fetches 3-14
3.6 Cache Coherency—MEI Protocol.3-15
3.6.1 MEI State Definitions ..3-15
3.6.2 MEI State Diagram ...3-16
3.6.3 MEI Hardware Considerations..3-17
3.6.4 Coherency Precautions.3-18
3.6.4.1 Coherency in Single-Processor Systems..3-18
3.6.5 Load and Store Coherency Summary .3-18
3.6.6 Atomic Memory References3-19
3.6.7 Cache Reaction to Specific Bus Operations.3-19
3.6.8 Operations Causing ARTRY Assertion ..3-21
3.6.9 Enveloped High-Priority Cache Block Push Operation 3-21
3.7 Cache Control Instructions .3-22
3.7.1 Data Cache Block Invalidate (dcbi) Instruction ...3-23
3.7.2 Data Cache Block Touch (dcbt) Instruction 3-23
3.7.3 Data Cache Block Touch for Store (dcbtst) Instruction 3-24
3.7.4 Data Cache Block Clear to Zero (dcbz) Instruction3-24
3.7.5 Data Cache Block Store (dcbst) Instruction 3-24
3.7.6 Data Cache Block Flush (dcbf) Instruction..3-24
3.7.7 Enforce In-Order Execution of I/O Instruction (eieio)..3-25
3.7.8 Instruction Cache Block Invalidate (icbi) Instruction ...3-25
3.7.9 Instruction Synchronize (isync) Instruction .3-25
3.8 Bus Operations Caused by Cache Control Instructions.3-25
3.9 Bus Interface..3-27
3.10 MEI State Transactions .3-28
4.1 Exception Classes ..4-2
4.1.1 Exception Priorities .4-7
4.1.2 Summary of Front-End Exception Handling..4-9
4.2 Exception Processing.4-10
4.2.1 Enabling and Disabling Exceptions.4-14
4.2.2 Steps for Exception Processing .4-15
4.2.3 Setting MSR[RI]..4-15
4.2.4 Returning from an Exception Handler 4-16
4.3 Process Switching4-16
4.4 Exception Latencies.4-17
4.5 Exception Definitions 4-17
4.5.1 Reset Exceptions (0x00100)4-18
4.5.1.1 Hard Reset and Power-On Reset .4-19
4.5.1.2 Soft Reset 4-20
4.5.2 Machine Check Exception (0x00200) .4-21
4.5.2.1 Machine Check Exception Enabled (MSR[ME] = 1) 4-22
4.5.2.2 Checkstop State (MSR[ME] = 0) 4-22
4.5.3 DSI Exception (0x00300)...4-23
4.5.4 ISI Exception (0x00400) 4-25
4.5.5 External Interrupt (0x00500).4-25
4.5.6 Alignment Exception (0x00600) 4-26
4.5.6.1 Integer Alignment Exceptions ..4-27
4.5.6.1.1 Page Address Translation Access ..4-28
4.5.6.2 Floating-Point Alignment Exceptions4-28
4.5.7 Program Exception (0x00700) ..4-29
4.5.7.1 IEEE Floating-Point Exception Program Exceptions 4-30
4.5.7.2 Illegal, Reserved, and Unimplemented Instructions
Program Exceptions ...4-30
4.5.8 Floating-Point Unavailable Exception (0x00800) ..4-31
4.5.9 Decrementer Exception (0x00900) .4-31
4.5.10 System Call Exception (0x00C00)4-31
4.5.11 Trace Exception (0x00D00)4-32
4.5.11.1 Single-Step Instruction Trace Mode ..4-33
4.5.11.2 Branch Trace Mode..4-33
4.5.12 Instruction TLB Miss Exception (0x01000) 4-33
4.5.13 Data TLB Miss on Load Exception (0x01100)4-34
4.5.14 Data TLB Miss on Store Exception (0x01200)4-35
4.5.15 Instruction Address Breakpoint Exception (0x01300)..4-35
4.5.16 System Management Interrupt (0x01400) ...4-37
5.1 MMU Features 5-2
5.1.1 Memory Addressing5-3
5.1.2 MMU Organization.5-3
5.1.3 Address Translation Mechanisms 5-8
5.1.4 Memory Protection Facilities5-10
5.1.5 Page History Information...5-11
5.1.6 General Flow of MMU Address Translation .5-11
5.1.6.1 Real Addressing Mode and Block Address Translation Selection ...5-11
5.1.6.2 Page Address Translation Selection5-12
5.1.7 MMU Exceptions Summary .5-14
5.1.8 MMU Instructions and Register Summary ..5-17
5.2 Real Addressing Mode..5-20
5.3 Block Address Translation .5-20
5.4 Memory Segment Model..5-21
5.4.1 Page History Recording .5-21
5.4.1.1 Referenced Bit.5-22
5.4.1.2 Changed Bit.5-23
5.4.1.3 Scenarios for Referenced and Changed Bit Recording..5-23
5.4.2 Page Memory Protection5-25
5.4.3 TLB Description..5-25
5.4.3.1 TLB Organization..5-25
5.4.3.2 TLB Entry Invalidation ..5-27
5.4.4 Page Address Translation Summary ...5-28
5.5 Page Table Search Operation .5-30
5.5.1 Page Table Search Operation—Conceptual Flow5-30
5.5.2 Implementation-Specific Table Search Operation ..5-33
5.5.2.1 Resources for Table Search Operations ...5-34
5.5.2.1.1 Data and Instruction TLB Miss Address Registers
(DMISS and IMISS)...5-36
5.5.2.1.2 Data and Instruction TLB Compare Registers (DCMP and ICMP).5-37
5.5.2.1.3 Primary and Secondary Hash Address Registers
(HASH1 and HASH2)5-37
5.5.2.1.4 Required Physical Address Register (RPA).5-38
5.5.2.2 Software Table Search Operation5-38
5.5.2.2.1 Flow for Example Exception Handlers 5-39
5.5.2.2.2 Code for Example Exception Handlers 5-44
5.5.3 Page Table Updates ...5-50
5.5.4 Segment Register Updates..5-50
6.1 Terminology and Conventions .6-1
6.2 Instruction Timing Overview ...6-3
6.3 Timing Considerations 6-5
6.3.1 General Instruction Flow6-6
6.3.2 Instruction Fetch Timing 6-9
6.3.2.1 Cache Arbitration 6-9
6.3.2.2 Cache Hit.6-9
6.3.2.3 Cache Miss ..6-10
6.3.3 Instruction Dispatch and Completion Considerations...6-11
6.3.3.1 Rename Register Operation...6-12
6.3.3.2 Instruction Serialization .6-13
6.3.3.3 Execution Unit Considerations..6-14
6.4 Execution Unit Timings.6-14
6.4.1 Branch Processing Unit Execution Timing ..6-14
6.4.1.1 Branch Folding 6-14
6.4.1.2 Static Branch Prediction .6-16
6.4.1.2.1 Predicted Branch Timing Examples.6-16
6.4.2 Integer Unit Execution Timing..6-18
6.4.3 Floating-Point Unit Execution Timing6-18
6.4.4 Load/Store Unit Execution Timing .6-18
6.4.5 System Register Unit Execution Timing6-18
6.5 Memory Performance Considerations.6-18
6.5.1 Copy-Back Mode 6-19
6.5.2 Write-Through Mode 6-19
6.5.3 Cache-Inhibited Accesses ..6-20
6.6 Instruction Scheduling Guidelines 6-20
6.6.1 Branch, Dispatch, and Completion Unit Resource Requirements ..6-21
6.6.1.1 Branch Resolution Resource Requirements.6-21
6.6.1.2 Dispatch Unit Resource Requirements 6-21
6.6.1.3 Completion Unit Resource Requirements6-22
6.7 Instruction Latency Summary 6-22
7.1 Signal Configuration .7-3
7.2 Signal Descriptions 7-4
7.2.1 Address Bus Arbitration Signals.7-4
7.2.1.1 Bus Request (BR)—Output.7-4
7.2.1.2 Bus Grant (BG)—Input7-5
7.2.1.3 Address Bus Busy (ABB) 7-5
7.2.1.3.1 Address Bus Busy (ABB)—Output .7-5
7.2.1.3.2 Address Bus Busy (ABB)—Input.7-6
7.2.2 Address Transfer Start Signals7-6
7.2.2.1 Transfer Start (TS) ..7-6
7.2.2.1.1 Transfer Start (TS)—Output 7-6
7.2.2.1.2 Transfer Start (TS)—Input..7-7
7.2.3 Address Transfer Signals .7-7
7.2.3.1 Address Bus (A[0–31]) 7-7
7.2.3.1.1 Address Bus (A[0–31])—Output..7-7
7.2.3.1.2 Address Bus (A[0–31])—Input.7-7
7.2.3.2 Address Bus Parity (AP[0–3]) 7-8
7.2.3.2.1 Address Bus Parity (AP[0–3])—Output 7-8
7.2.3.2.2 Address Bus Parity (AP[0–3])—Input...7-8
7.2.3.3 Address Parity Error (APE)—Output..7-8
7.2.4 Address Transfer Attribute Signals.7-9
7.2.4.1 Transfer Type (TT[0–4])..7-9
7.2.4.1.1 Transfer Type (TT[0–4])—Output7-9
7.2.4.1.2 Transfer Type (TT[0–4])—Input ..7-9
7.2.4.2 Transfer Size (TSIZ[0–2])—Output ..7-12
7.2.4.3 Transfer Burst (TBST) ...7-13
7.2.4.3.1 Transfer Burst (TBST)—Output .7-13
7.2.4.3.2 Transfer Burst (TBST)—Input 7-13
7.2.4.4 Transfer Code (TC[0–1])—Output .7-14
7.2.4.5 Cache Inhibit (CI)—Output ..7-14
7.2.4.6 Write-Through (WT)—Output..7-14
7.2.4.7 Global (GBL)7-15
7.2.4.7.1 Global (GBL)—Output .7-15
7.2.4.7.2 Global (GBL)—Input .7-15
7.2.4.8 Cache Set Entry (CSE[0–1])—Output .7-15
7.2.5 Address Transfer Termination Signals7-15
7.2.5.1 Address Acknowledge (AACK)—Input..7-16
7.2.5.2 Address Retry (ARTRY)7-16
7.2.5.2.1 Address Retry (ARTRY)—Output.7-16
7.2.5.2.2 Address Retry (ARTRY)—Input 7-17
7.2.6 Data Bus Arbitration Signals.7-17
7.2.6.1 Data Bus Grant (DBG)—Input .7-17
7.2.6.2 Data Bus Write Only (DBWO)—Input ...7-18
7.2.6.3 Data Bus Busy (DBB) 7-18
7.2.6.3.1 Data Bus Busy (DBB)—Output ..7-18
7.2.6.3.2 Data Bus Busy (DBB)—Input.7-18
7.2.7 Data Transfer Signals 7-19
7.2.7.1 Data Bus (DH[0–31], DL[0–31]) 7-19
7.2.7.1.1 Data Bus (DH[0–31], DL[0–31])—Output..7-19
7.2.7.1.2 Data Bus (DH[0–31], DL[0–31])—Input.7-20
7.2.7.2 Data Bus Parity (DP[0–7]) 7-20
7.2.7.2.1 Data Bus Parity (DP[0–7])—Output 7-20
7.2.7.2.2 Data Bus Parity (DP[0–7])—Input.7-20
7.2.7.3 Data Parity Error (DPE)—Output...7-21
7.2.7.4 Data Bus Disable (DBDIS)—Input.7-21
7.2.8 Data Transfer Termination Signals .7-21
7.2.8.1 Transfer Acknowledge (TA)—Input..7-22
7.2.8.2 Data Retry (DRTRY)—Input7-22
7.2.8.3 Transfer Error Acknowledge (TEA)—Input7-23
7.2.9 System Status Signals7-23
7.2.9.1 Interrupt (INT)—Input...7-23
7.2.9.2 System Management Interrupt (SMI)—Input ..7-24
7.2.9.3 Machine Check Interrupt (MCP)—Input.7-24
7.2.9.4 Checkstop Input (CKSTP_IN)—Input 7-24
7.2.9.5 Checkstop Output (CKSTP_OUT)—Output...7-25
7.2.9.6 Reset Signals 7-25
7.2.9.6.1 Hard Reset (HRESET)—Input7-25
7.2.9.6.2 Soft Reset (SRESET)—Input 7-26
7.2.9.7 Processor Status Signals.7-26
7.2.9.7.1 Quiescent Request (QREQ) ..7-26
7.2.9.7.2 Quiescent Acknowledge (QACK).7-26
7.2.9.7.3 Reservation (RSRV)—Output 7-27
7.2.9.7.4 Time Base Enable (TBEN)—Input7-27
7.2.9.7.5 TLBI Sync (TLBISYNC) .7-27
7.2.10 COP/Scan Interface...7-28
7.2.11 Pipeline Tracking Support..7-28
7.2.12 Clock Signals ..7-29
7.2.12.1 System Clock (SYSCLK)—Input...7-30
7.2.12.2 Test Clock (CLK_OUT)—Output ..7-30
7.2.12.3 PLL Configuration (PLL_CFG[0–3])—Input .7-30
7.2.13 Power and Ground Signals.7-32
Chapter 8
System Interface Operation
8.1 Overview .8-1
8.1.1 Operation of the Instruction and Data Caches .8-2
8.1.2 Operation of the System Interface8-4
8.1.2.1 Optional 32-Bit Data Bus Mode .8-5
8.1.3 Direct-Store Accesses .8-6
8.2 Memory Access Protocol 8-6
8.2.1 Arbitration Signals 8-7
8.2.2 Address Pipelining and Split-Bus Transactions.8-8
8.3 Address Bus Tenure ..8-9
8.3.1 Address Bus Arbitration.8-9
8.3.2 Address Transfer .8-11
8.3.2.1 Address Bus Parity8-13
8.3.2.2 Address Transfer Attribute Signals.8-13
8.3.2.2.1 Transfer Type (TT[0–4]) Signals8-13
8.3.2.2.2 Transfer Size (TSIZ[0–2]) Signals.8-13
8.3.2.3 Burst Ordering During Data Transfers.8-14
8.3.2.4 Effect of Alignment in Data Transfers (64-Bit Bus).8-15
8.3.2.5 Effect of Alignment in Data Transfers (32-Bit Bus).8-17
8.3.2.5.1 Alignment of External Control Instructions.8-19
8.3.2.6 Transfer Code (TC[0–1]) Signals ...8-20
8.3.3 Address Transfer Termination .8-20
8.4 Data Bus Tenure..8-22
8.4.1 Data Bus Arbitration .8-22
8.4.1.1 Using the DBB Signal 8-23
8.4.2 Data Bus Write Only.8-24
8.4.3 Data Transfer...8-24
8.4.4 Data Transfer Termination.8-25
8.4.4.1 Normal Single-Beat Termination 8-26
8.4.4.2 Data Transfer Termination Due to a Bus Error 8-29
8.4.5 Memory Coherency—MEI Protocol ...8-30
8.5 Timing Examples.8-32
8.6 Optional Bus Configurations ..8-38
8.6.1 32-Bit Data Bus Mode..8-38
8.6.2 No-DRTRY Mode.8-40
8.6.3 Reduced-Pinout Mode ..8-40
8.7 Interrupt, Checkstop, and Reset Signals..8-41
8.7.1 External Interrupts .8-41
8.7.2 Checkstops.8-41
8.7.3 Reset Inputs .8-41
8.7.4 System Quiesce Control Signals 8-42
8.8 Processor State Signals..8-42
8.8.1 Support for the lwarx/stwcx. Instruction Pair8-42
8.8.2 TLBISYNC Input 8-42
8.9 IEEE 1149.1-Compliant Interface .8-43
8.9.1 IEEE 1149.1 Interface Description8-43
8.10 Using Data Bus Write Only8-43
9.1 Dynamic Power Management ..9-1
9.2 Programmable Power Modes9-1
9.2.1 Power Management Modes ..9-3
9.2.1.1 Full-Power Mode with DPM Disabled.9-3
9.2.1.2 Full-Power Mode with DPM Enabled..9-3
9.2.1.3 Doze Mode 9-4
9.2.1.4 Nap Mode9-4
9.2.1.5 Sleep Mode9-5
9.2.2 Power Management Software Considerations9-6
A.1 Instructions Sorted by Mnemonic...A-1
A.2 Instructions Sorted by Opcode A-9
A.3 Instructions Grouped by Functional Categories A-17
A.4 Instructions Sorted by Form ..A-28
A.5 Instruction Set Legend..A-39
C.1 PowerPC 603 Microprocessor Hardware Considerations.. C-1
C.1.1 Hardware Support for Direct-Store Accesses . C-1
C.1.1.1 Extended Address Transfer Start (XATS)? C-2
C.1.1.1.1 Extended Address Transfer Start (XATS)—Output ... C-2
C.1.1.1.2 Extended Address Transfer Start (XATS)—Input. C-2
C.1.2 Direct-Store Protocol Operation? C-2
C.1.2.1 Direct-Store Transactions? C-4
C.1.2.1.1 Store Operations. C-5
C.1.2.1.2 Load Operations. C-5
C.1.2.2 Direct-Store Transaction Protocol Details? C-6
C.1.2.2.1 Packet 0? C-7
C.1.2.2.2 Packet 1? C-8
C.1.2.3 I/O Reply Operations? C-8
C.1.2.4 Direct-Store Operation Timing? C-10
C.1.3 CSE Signal . C-12
C.1.4 PowerPC 603 Processor Bus Clock Multiplier Configuration... C-12
C.1.5 PowerPC 603 Processor Cache Organization . C-13
C.1.5.1 Instruction Cache Organization . C-14
C.1.5.2 Data Cache Organization . C-14
C.1.6 PLL Configuration (PLL_CFG[0–3])—Input. C-15
C.1.7 Address Pipelining and Split-Bus Transactions.. C-15
C.1.8 Data Bus Arbitration? C-16
C.2 PowerPC 603 Processor Software Considerations.. C-16
C.2.1 Direct-Store Interface Address Translation? C-16
C.2.1.1 Direct-Store Segment Translation Summary Flow.. C-17
C.2.1.2 Direct-Store Interface Accesses . C-18
C.2.1.3 Direct-Store Segment Protection ... C-18
C.2.1.4 Instructions Not Supported in Direct-Store Segments .. C-19
C.2.1.5 Instructions with No Effect in Direct-Store Segments.. C-19
C.2.2 Store Instruction Latency .. C-19
C.2.3 Instruction Execution by System Register Unit .. C-20
C.2.4 Machine Check Exception (0x00200) C-21
C.2.5 Instruction Address Breakpoint Exception (0x01400). C-21
C.2.6 Cache Control Instructions C-21