本文基于數(shù)據(jù)驅(qū)動(dòng)原理提出并用 FPGA 實(shí)現(xiàn)了MPEG-2 MP@HL 的視頻解碼器。該
解碼器中的各個(gè)模塊具有高內(nèi)聚，低耦合的特點(diǎn)。只要各個(gè)模塊符合數(shù)據(jù)驅(qū)動(dòng)的工作方式，模塊就能自我正常工作。由于視頻數(shù)據(jù)和控制數(shù)據(jù)分開(kāi)，能夠節(jié)省各個(gè)模塊占用的存儲(chǔ)器資源。另外，對(duì)SDRAM 讀寫(xiě)上作了一定的優(yōu)化。
關(guān)鍵詞：數(shù)據(jù)驅(qū)動(dòng)；MPEG-2；高清晰電視；視頻解碼器
An compact and high efficiency MPEG-2 MP＠HL video decoder Zhao Bo，Chen Guang Hua
Abstract：A compact and high efficiency MPEG-2 MP@HL video decoder is presented based on data driven. The modules of decoder are of high cohesion and low coupling. If the state of module accords to the working modes of data driven, the module will work spontaneously. Because of depart of video data and control data，the decoder can reduce storage of all modules and hardware spending. In addition the decoder has a certain extent optimize of SDRAM.