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AD5694R FMC-SDP轉接器和評估板/Xilinx KC705參考設計

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資料介紹

This version (09 Jan 2021 00:51) was approved by Robin Getz.The Previously approved version (01 Oct 2013 11:35) is available.

AD5694R FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design
- Supported Devices
- Evaluation Boards
Overview
- More information
Getting Started
Run the Demonstration Project
More information

AD5694R FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

Supported Devices

AD5694R

Evaluation Boards

EVAL-AD5694RSDZ

Overview

This document presents the steps to setup an environment for using the EVAL-AD5694RSDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5694RSDZ Evaluation Board with the Xilinx KC705 board.

For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:

1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
2. The component SDP compatible product evaluation board
3. Corresponding PC software ( shipped with the product evaluation board)

The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.

Note: it is expected that the analog performance on the two platforms may differ.

28 Sep 2012 10:32 · Adrian Costina

Below is presented a picture of SDP-B Controller Board with the EVAL-AD5694RSDZ Evaluation Board.

The EVAL-AD5694RSDZ evaluation board is designed to help customers quickly prototype new AD5694R/ AD5694R circuits and reduce design time.

The AD5694R nanoDAC is a quad, 12-bit, rail-to-rail, voltage output DAC. The device includes a 2.5V, 2ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5V (gain=1) or 5V (gain=2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design and exhibits less than 0.1% FSR gain error and 1.5mV offset error performance. The device is available in a 3mm X 3mm LFCSP and a TSSOP package.

More information

AD5694R Product Info - pricing, samples, datasheet
EVAL-AD5694RSDZ evaluation board user guide
Xilinx KC705 FPGA board

Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Required Hardware

Xilinx KC705 FPGA board
FMC-SDP adapter board
EVAL-AD5694R evaluation board

Required Software

Xilinx ISE 14.6.
UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200.
The EVAL-AD5694R reference project for Xilinx KC705 FPGA.

Downloads

AD5694R Driver: https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5686
AD5694R Commands: https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5686
Xilinx Boards Common Drivers: https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
EDK KC705 Reference project: https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705

Run the Demonstration Project

Hardware setup

Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.

Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
Connect the JTAG and UART cables to the KC705 and power up the FPGA board.

To power on the EVAL-AD5694R evaluation board, you need to apply +6V supply voltage to J3 connector of the board.

Reference Project Overview

The following commands were implemented in this version of EVAL-AD5694R reference project for Xilinx KC705 FPGA board.

Command	Description
help?	Displays all available commands.
reset!	Activate a power-on reset.
load=	Loads selected DAC input register with a given value. Accepted values: channel: 0 - select channel A. 1 - select channel B. 2 - select channel C. 3 - select channel D. value: 0 .. 4095 - value to be written in register.
update=	Update the selected DAC channel with the input register. Accepted values: channel: 0 - select channel A. 1 - select channel B. 2 - select channel C. 3 - select channel D. 4 - select all channels.
loadAndUpdate=	Loads and updates the selected DAC with a given value. Accepted values: channel: 0 - select channel A. 1 - select channel B. 2 - select channel C. 3 - select channel D. value: 0 .. 4095 - value to be written in register.
pwrMode=	Set up the Power Mode of a selected channel. Accepted values: channel: 0 - select channel A. 1 - select channel B. 2 - select channel C. 3 - select channel D. 4 - select all channels. power mode: 0 - normal operation. 1 - 1KOhm to GND. 2 - 100KOhms to GND. 3 - three-state.
pwrMode?	Displays the power mode for one selected DAC. Accepted values: channel: 0 - select channel A. 1 - select channel B. 2 - select channel C. 3 - select channel D.
ldacMask=	Set up the LDAC mask register. Accepted values: channel: 0 - select channel A. 1 - select channel B. 2 - select channel C. 3 - select channel D. 4 - select all channels. set/reset mask: 0 - reset LDAC mask for the selected channel. 1 - set LDAC mask for the selected channel.
ldacMask?	Displays the LDAC register.
intRef=	Turns ON or OFF the internal reference. Accepted values: 0 - turns OFF the internal reference.(default) 1 - turns ON the internal reference.
intRef?	Displays the status of the internal reference.
ldacPin=	Sets the output value of LDAC pin. Accepted values: 0 - sets LDAC pin low.(default) 1 - sets LDAC pin high.
ldacPin?	Displays the value of LDAC pin.

Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.

The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral.

Software Project Setup

The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design:

First download the KC705 Reference project from Github on your computer. You can do this by clonning this repository: https://github.com/analogdevicesinc/fpgahdl_xilinx.

From this entire repository you will use cf_sdp_kc705 folder. This is common for all KC705 projects.

Open the Xilinx SDK. When the SDK starts, it asks you to provide a folder where to store the workspace. Any folder can be provided. Make sure that the path where it is located does not contain any spaces.
In the SDK select the File→Import menu option to import the software projects into the workspace.

In the Import window select the General→Existing Projects into Workspace option.

In the Import Projects window select the cf_sdp_kc705 folder as root directory and check the Copy projects into workspace option. After the root directory is chosen the projects that reside in that directory will appear in the Projects list. Press Finish to finalize the import process.

The Project Explorer window now shows the projects that exist in the workspace without software files.

Now the software must be added in your project. For downloading the software, you must use 3 links from Github given in Downloads section. From there you'll download the specific driver, the specific commands and the Xilinx Boards Common Drivers(which are commons for all Xilinx boards). All the software files downloaded must be copied in src folder from sw folder.

Before compilation in the file called Communication.h you have to uncomment the name of the device that you currently use. In the picture below there is an example of this, which works only with AD5629R project. For another device, uncomment only the respective name. You can have one driver working on multiple devices, so the drivers's name and the uncommented name may not be the same for every project.

The SDK should automatically build the project and the Console window will display the result of the build. If the build is not done automatically, select the Project→Build Automatically menu option.
If the project was built without any errors, you can program the FPGA and run the software application.

13 Aug 2013 09:22 · Lucian Sin