• AD7693

• EVAL-AD7693SDZ

This document presents the steps to setup an environment for using the EVAL-AD7693SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD7693SDZ Evaluation Board with the Xilinx KC705 board.

Below is presented a picture of SDP-B Controller Board with the EVAL-AD7693SDZ Evaluation Board.

The AD7693 is a 16-bit, successive approximation analog-to-digital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The reference voltage, VREF, is applied externally and can be set up to the supply voltage, VDD. On the CNV rising edge, it samples the voltage difference between the IN+ and IN? pins. The voltages on these pins swing in opposite phase between 0 V and VREF about VREF/2. Its power scales linearly with throughput.

The EVAL-AD7693SDZ evaluation board is a member of a growing number of boards available for the SDP. It was designed to help customers evaluate performance or quickly prototype new AD7693 circuits and reduce design time.

• AD7693 Product Info - pricing, samples, datasheet
• EVAL-AD7693SDZ evaluation board user guide
• Xilinx KC705 FPGA board

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

• Xilinx KC705 FPGA board
• FMC-SDP adapter board
• EVAL-AD7693SDZ evaluation board

• Xilinx ISE 13.2
• A UART terminal (ex. TeraTerm / Hyperterminal).

• Reference Design Files

The following table presents a short description the reference design archive contents.

• Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
• Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
• Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).

• Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
• Power the ADI evaluation board.
• Start a UART terminal and set the baud rate to 115200 bps.

At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the data_capture.bat script located in the DataCapture folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the Acquisition.csv file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.