| Function | Clock generator |
| Number of outputs | 1 |
| Output frequency (Max) (MHz) | 683.28 |
| Core supply voltage (V) | 3.3 |
| Output supply voltage (V) | 3.3 |
| Input type | XTAL, LVCMOS |
| Output type | LVCMOS, LVDS, LVPECL |
| Operating temperature range (C) | -40 to 85 |
| Features | Pin programmable |
| Rating | Catalog |
- One Crystal/LVCMOS Reference Input Including 24.8832 MHz, 25 MHz,
and 26.5625 MHz - Input Frequency Range: 21.875 MHz to
28.47 MHz - On-Chip VCO Operates in Frequency Range of 1.75 GHz to 2.05 GHz
- 1x Output Available:
- Pin-Selectable Between LVPECL, LVDS, or 2-LVCMOS; Operates at 3.3 V
- LVCMOS Bypass Output Available
- Output Frequency Selectable by /1, /2, /3, /4, /6, /8 from the
Output Divider - Supports Common LVPECL/LVDS Output Frequencies:
- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz,
150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 187.5 MHz, 200 MHz, 212.5 MHz,
250 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz, 625 MHz
- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz,
- Supports Common LVCMOS Output Frequencies:
- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz,
150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 187.5 MHz, 200 MHz,
212.5 MHz, 250 MHz
- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz,
- Output Frequency Range: 43.75 MHz to 683.264 MHz
- Internal PLL Loop Bandwidth: 400 kHz
- High-Performance PLL Core:
- Phase Noise typically at –146 dBc/Hz at 5-MHz Offset
for 625-MHz LVPECL Output - Random Jitter typically at 0.509 ps, RMS (10 kHz to 20 MHz)
for 625-MHz LVPECL Output
- Phase Noise typically at –146 dBc/Hz at 5-MHz Offset
- Output Duty Cycle Corrected to 50% (± 5%)
- Divider Programming Using Control Pins:
- Two Pins for Prescaler/Feedback Divider
- Three Pins for Output Divider
- Two Pins for Output Select
- Chip Enable and Device Reset Control Pins Available
- 3.3-V Core and I/O Power Supply
- Industrial Temperature Range: –40°C to +85°C
- 5-mm × 5-mm, 32-pin, QFN (RHB) Package
- ESD Protection Exceeds 2 kV (HBM)
The CDCM61001 is a highly versatile, low-jitter frequency synthesizer that can generate low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal or LVCMOS input for a variety of wireline and data communication applications. The CDCM61001 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61001 is available in a small, 32-pin, ?5-mm × 5-mm QFN package.
The CDCM61001 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with one universal output buffer that can be configured to be LVPECL, LVDS, or LVCMOS compatible. The universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading in order to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output has an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and divider are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUT with respect to fIN. For a configuration setting for common wireline and datacom applications, refer to. For other applications, use to calculate the exact crystal oscillator frequency required for the desired output.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. shows a high-level block diagram of the CDCM61001.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to +85°C.
